# 0x213 Digital Circuits

## 1. Boolean Algebra

some Boolean algebra help to simplify Boolean equations while maintaining semantics

Some Axioms are

• $$0 \cdot 0 = 0, 1 + 1 = 1$$
• $$1 \cdot 1 = 1, 0 + 0 = 0$$
• $$0 \cdot 1 = 1 \cdot 0 = 0, 1 + 0 = 0 + 1 = 1$$

where $$\cdot, +$$ indicates AND and OR respectively

Based on those axioms we derived a few theorems

• (commutativity) $$B \cdot C = C \cdot B$$
• (associativity) $$(B \cdot C) \cdot D = B \cdot (C \cdot D)$$
• (distributivity) $$(B \cdot C) + (B \cdot D) = B \cdot (C + D)$$
• (covering) $$B \cdot (B + C) = B, B + (B \cdot C) = B$$

There is also the Bubble pushing rule by applying De Morgan's theorem visually

## 2. Combinational logic

combinational logic are memoryless and outputs are determined by inputs only. It should not contain cycles

### 2.1. Gates

Some major gates are adder, multiplexer and decoder

### 2.2. Timing

There are delay in gates caused by capacitance, resistance and also speed of light.

• Propgation delay: max delay from input to output
• contamination delay: min delay from input to output

propagation time of major gates can be looked up in some timing spec in the order of picoseconds (10**-12 second)

A relevant behavior caused by this delay is called glitches where a single input change causes multiple output changes, it is because different path has different delays.

Note that glitches are not a big issue in synchronous design

## 3. Sequential Logic

sequential logic has memory, outputs are determined by inputs and memory

### 3.1. Latch

Latch (SR Latch) two nor gate (active high) two nand gate(active low)

Latch (Gated SR Latch) add a gate to SR Latch

Latch (Gated D Latch) S, R are merged into D bus